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40-Channel, 3 V/5 V, Single-Supply,
12-Bit, Voltage Output DAC
AD5381
FEATURES
Guaranteed monotonic
INL error: ±1 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: –40°C to +85°C
Rail-to-rail output amplifier
Power-down
Package type: 100-lead LQFP (14 mm × 14 mm)
User Interfaces:
Parallel
Serial (SPI/QSPI/MICROWIRE/DSP compatible,
featuring data readback)
I
2
C compatible
Rev.
A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
INTEGRATED FUNCTIONS
Channel monitor
Simultaneous output update via LDAC
Clear function to user programmable code
Amplifier boost mode to optimize slew rate
User programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitors
APPLICATIONS
Variable optical attenuators (VOA)
Level setting (ATE)
Optical micro-electro-mechanical systems (MEMs)
Control systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
R
R
VOUT0
DAC 0
DAC
REG 0
INPUT
REG 0
12
12
12
12
12
12
m REG 0
c REG 0
1.25V/2.5V
REFERENCE
POWER-ON
RESET
39-TO-1
MUX
R
R
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
DAC 1
DAC
REG 1
INPUT
REG 1
12
12
12
12
12
12
m REG 1
c REG 1
R
R
VOUT6
DAC 6
DAC
REG 6
INPUT
REG 6
12
12
12
12
12
12
m REG 6
c REG 6
R
R
VOUT7
VOUT8
DAC 7
DAC
REG 7
INPUT
REG 7
12
12
12
12
12
12
m REG 7
c REG 7
×5
0
FIFO
+
STATE
MACHINE
+
CONTROL
LOGIC
INTERFACE
CONTROL
LOGIC
DB11/(DIN/SDA)
DB10/(SCLK/SCL)
DB9/(SPI/I2C)
DB8
A5
A0
V
OUT
0………V
OUT
38
REG 0
REG 1
RESET
BUSY
CLR
PD
SER/PAR
FIFO EN
CS/(SYNC/AD 0)
WR/(DCEN/AD 1)
SDO
VOUT 39/MON_OUT
LDAC
VOUT38
DVDD (×3)
DGND (×3)
AVDD (×5)
AGND (×5)
DAC GND (×5)
REFGND
REFOUT/REFIN
SIGNAL GND (×5)
AD5381
DB0
Figure 1.
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